MEN Mikro D602

Specification

CPU:

3x PowerPC® 750 GL

• Scalable performance
  
• Up to 900MHz processor core frequency
  
• Superscalar
  
• Classic PowerPC® FPU, MMU
  
• CPU bus to FPGA: 100-MHz/64-bit

Lock-step operation

• All CPUs do the same thing at the same time
• 2-out-of-3 voting in FPGA with CPU bus clock speed (100MHz)
  
• Software-assisted resynchronization
  
• No functional interruption in case of an SEU inside the CPU
  

Chipset:

North- and Southbridge realized in FPGA

Memory:

2x 32 kB L1 cache, 1MB L2 cache integrated in each CPU
3 independent banks of 512MB DDR SDRAM system memory, FPGA-controlled

• 100MHz memory bus frequency (32 bit)
  
• Up to 800 MB/s
  
• 2-out-of-3 voting in FPGA
  
• Scrubbing to prevent accumulation of SEU
  
• No functional interruption in case of an SEU inside the memory

2 independent banks of 256MB Flash, FPGA-controlled

• Primary and backup Flash banks contain the same data, auto-selection by boot loader
• ECC protection

1MB FRAM, ECC protection
4KB serial EEPROM for production data (serial number etc.)

I/O:

All I/O realized in FPGA and available at rear I/O
Sextuple UART

• E.g., for communication with other D602
  
• Data rates up to 460,800 Baud for each channel
  
• Handshake lines: none

RS232 UART

• Data rates up to 460,800 Baud
  
• 2x 256 Byte transmit/receive buffer
  
• Handshake lines: none

PCI bus
I²C bus

Mezzanine Slots:

Two PMC slots

• 32 bit/33 MHz, 3.3V V(I/O)
  
• PMC1 with front I/O, revisions -02 and later also with rear I/O
  
• PMC2 customized for AFDX® PMC with rear I/O only

Miscellaneous:

Voltage monitoring
Temperature monitoring
Watchdog
Reset signal control
Control of redundant power supplies
Sleep mode

• Lowers power consumption in case of primary power supply interruption
  
• Power failure indicated through signals from backplane
  
• Supports power interruptions specified in Airbus directive ABD0100.1.9
  
• CPUs and memory can be put into sleep mode

Redundant clock generation
Connection with second D602 possible (with special backplane)

• Control of shared outputs
• Exchange of state information
  
• BMC and 6x UART link

CompactPCI® Bus:

Compliance with CompactPCI® Core Specification PICMG 2.0 R3.0
System slot
32-bit/33-MHz PCI-to-PCI bridge
V(I/O): +3.3V

Electrical:

Dual power input from CompactPCI® bus

• 2x 3.3V, 2x 5V
  
• Standard backplane supplies both input rails with power
  
• Continued operation if one power input fails (or is not present)
  
• Separate power supplies for the three CPUs and the three main memory banks

Supply voltage/power consumption:

• 30W
  
• 15W in sleep mode

Mechanical:

Dimensions: conforming to CompactPCI® specification for 6U boards
Front panel: 4HP with ejector
Weight: 640g (with heat sink)

Environmental:

Temperature range (operation): -40 to +55°C with qualified components
Temperature range (storage): -40 to +85°C
Relative humidity range (operation): max. 95% non-condensing
Relative humidity range (storage): max. 95% non-condensing
Altitude: -300m to + 20,000m
Shock: 15g/11ms
Bump: 10g/16ms
Vibration (sinusoidal): 1g/10 to 150Hz
Conformal coating on request
All components soldered

MTBF:

46,000h @ 40°C according to MIL.HDBK-217FN2 with modifications.
Weighted mean figure for 65% operation in AIC (air inhabited cargo) and 35% operation in GF (ground fixed) conditions

Safety:

Erroneous behavior of CPU/memory subsystem < 1E-8 / h, considering hardware failures and worst-case SEU environment
PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers

EMC:

Conforming to EN 55022 (radio disturbance), EN 55024 / EN 61000-4-2 (electrostatic discharge immunity) and EN 55024 / EN 61000-4-3 (electromagnetic field immunity)

BIOS:

MENMON™

Software:

VxWorks®, VxWorks®/Cert
PikeOS

ROHS Status:

This product is lead free/ROHS compliant.