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Men Mikro

Men Mikro F206N

3U CompactPCI® Nios® II Slave Board

Nios® II Soft Processor & Altera® Cyclone™ FPGA With 144000 Gates
 
Men Mikro F206N 3U CompactPCI Nios II Slave Board
  
  • 32-bit/33-MHz CompactPCI®
  • Peripheral slot function
  • FPGA 12,000 LEs (approx.144,000 gates)
  • Nios® II soft processor
  • 32 MB SDRAM, 2 MB Flash
  • Flexible FPGA-Flash structure
  • Open platform FPGA development package
  • Support of Wishbone and Avalon® bus
  • -40 to +85°C with qualified components



Datasheet/Manual:

MEN F206N datasheet in PDF format Datasheet in PDF format
Manual available on request Manual available on request

 

Introduction

The F206N is a 3U CompactPCI® card with an on-board Altera® Cyclone™ FPGA and the integrated Nios® II soft processor. It is designed for final use in volume in an application and it acts at the same time as the standard FPGA development platform for this application.

Due to its multitude of directly accessible I/O pins the F206N can be used as a universal FPGA platform. With the Nios® II CPU inside the FPGA, the F206N can for example act as an intelligent slave on the CompactPCI® bus. In any case the F206N supports a nearly endless range of applications. Examples may include functions such as an intelligent 8-channel CAN controller with DMA and local protocol stack, realtime Ethernet controller, analog front end with DSPlike pre-computing, intelligent counter, intelligent HDLC interface etc.

The Cyclone™ FPGA acts as the main controller. It supports a 32-bit/33-MHz CompactPCI® bus, controls the SDRAM memory and has read/write access to the Flash memory. The special FPGA-Flash structure provides initial programming using a boundary scan interface and later, with a configured FPGA, the device may be updated at any time with data from the CompactPCI® bus. The FPGA also controls four status LEDs and up to 79 user-defined I/O pins.

A total of 32MB soldered SDRAM and 2MB Flash back the potential computing functionality of the F206N. The F206N is designed for use in rugged environments. For example, all components are specified for an operation temperature of -40 to +85°C. For development of the application MEN provides a Nios® - CompactPCI® open platform FPGA development package that includes a sample design with an internal PCI system unit, integrating the standard Wishbone and the Altera® Avalon® bus.
 
 

Specification
CPU:

Nios® II soft processor
o 33MHz
Memory:

512 bytes instruction cache and 512 bytes data cache integrated in Nios® II
32MB SDRAM system memory
o Soldered
o 133MHz memory bus frequency
2MB boot Flash
I/O:

One RS232 UART (COM10)
o D-Sub connector at front panel
o Data rates up to 115.2kbits/s
o 60-byte transmit/receive buffer
o Handshake lines: full support
o For debugging

Three 10-pin connectors
o For FPGA-controlled functions
o For use of one additional SA-Adapter™
o One receptacle for direct SA-Adapter™ connection at the front
o Two receptacles for direct connection of long SA-Adapters™ at the front (instead of short SA-Adapters™)
o Different physical layers through SA-Adapters™: RS232, RS422, RS485, Ethernet, CAN bus, binary I/O
FPGA:

Standard factory FPGA configuration:
o Nios® II soft processor
o 16Z014_PCI - PCI to Wishbone interface
o 16Z052_GIRQ - Global Interrupt Controller (Nios®)
o 16Z052_GIRQ - Global Interrupt Controller (CPU)
o 16Z069_RST - Reset Controller
o 16Z043_SDRAM - SDRAM controller (32MB)
o 16Z045_FLASH - Flash interface
o 16Z025_UART - UART controller (controls COM10)
The FPGA offers the possibility to add customized I/O functionality
Miscellaneous:

Four user LEDs, FPGA-controlled
Local PCI Bus:

32-bit/33-MHz, 3.3V V(I/O)
Compliant with PCI Specification 2.2
CompactPCI® Bus:

Compliance with CompactPCI® Core Specification PICMG 2.0 R3.0
Peripheral slot
32-bit/33-MHz PCI
V(I/O): +3.3V
Only one slot required on 3U CompactPCI® backplane
More supplementary CompactPCI® slots required depending on SA-Adapters™
Electrical:

Supply voltage/power consumption:
o +5V (-3%/+5%), current depends only on mounted SA-Adapters™
o +3.3V (-3%/+5%), 500mA typ.
MTBF: 308,000h @ 40°C (derived from MIL-HDBK-217F)
Mechanical:

Dimensions: conforming to CompactPCI® specification for 3U boards
Single 3U front panel slot for up to two 9-pin D-Sub connectors
Weight: 165g
Environmental:

Temperature range (operation):
o -40..+85°C (qualified components)
o Airflow: min. 10m³/h
Temperature range (storage): -40..+85°C
Relative humidity (operation): max. 95% non-condensing
Relative humidity (storage): max. 95% non-condensing
Altitude: -300m to + 3,000m
Shock: 15g/11ms
Bump: 10g/16ms
Vibration (sinusoidal): 2g/10..150Hz
Conformal coating on request
Safety:

PCB manufactured with a flammability rating of 94V-0 by UL recognized manufacturers
EMC:

Tested according to EN 55022 (radio disturbance), IEC1000-4-2 (ESD) and IEC1000-4-4 (burst)
Software Support:

Nios® sample design for Quartus® II development tools
Flash update tools for Windows®, Linux, VxWorks®
Driver software depending on implemented FPGA functions
ROHS Status:

This product is lead free/ROHS compliant.

Ordering Details:
Board:

02F206N00 F206N, 3U CompactPCI®, 1-slot FPGA-based intelligent Nios® II slave board, 32MB DRAM, 2MB Flash, 1x RS232 (08SA01-06) mounted, FPGA for user-defined functions, operation temperature -40..+85°C

16F206N00 Nios®-CompactPCI® Open Platform FPGA Development Package (MEN) (without Altera® Quartus® II)

Please refer to datasheet for further information.
Accessories:

N/A
Further Information:

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